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MCP2030
REGISTER 5-2:
CONFIGURATION REGISTER 1 (ADDRESS: 0001)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATOUT
DATOUT
LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0
R1PAR
bit 8
1
0
bit 0
bit 8-7
bit 6-1
bit 0
Legend:
DATOUT<1:0>: LFDATA Output type bit
00 = Demodulated output
01 = Carrier clock output
10 = RSSI output
11 = RSSI output
LCXTUN<5:0>: LCX Tuning Capacitance bit
000000 = +0 pF (Default)
:
111111 = +63 pF
R1PAR : Register 1 Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 5-3:
CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RSSIFET
bit 8
CLKDIV
LCYTUN5 LCYTUN4 LCYTUN3 LCYTUN2 LCYTUN1 LCYTUN0
R2PAR
bit 0
bit 8
bit 7
bit 6-1
bit 0
Legend:
RSSIFET : Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)
1 = Pull-down RSSI MOSFET on
0 = Pull-down RSSI MOSFET off
CLKDIV: Carrier Clock Divide-by bit
1 = Carrier clock/4
0 = Carrier clock/1
LCYTUN<5:0>: LCY Tuning Capacitance bit
000000 = +0 pF (Default)
:
111111 = +63 pF
R2PAR : Register 2 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
DS21981A-page 52
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
? 2005 Microchip Technology Inc.
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